diff --git a/bios/gdt.asm b/bios/gdt.asm
index 896b04f..0322a53 100644
--- a/bios/gdt.asm
+++ b/bios/gdt.asm
@@ -64,27 +64,6 @@ gdt:
 .null equ $ - gdt
     dq 0
 
-.lm64_code equ $ - gdt
-istruc GDTEntry
-    at GDTEntry.limitl, dw 0
-    at GDTEntry.basel, dw 0
-    at GDTEntry.basem, db 0
-    at GDTEntry.attribute, db gdt_attr.present | gdt_attr.user | gdt_attr.code
-    at GDTEntry.flags__limith, db gdt_flag.long_mode
-    at GDTEntry.baseh, db 0
-iend
-
-.lm64_data equ $ - gdt
-istruc GDTEntry
-    at GDTEntry.limitl, dw 0
-    at GDTEntry.basel, dw 0
-    at GDTEntry.basem, db 0
-; AMD System Programming Manual states that the writeable bit is ignored in long mode, but ss can not be set to this descriptor without it
-    at GDTEntry.attribute, db gdt_attr.present | gdt_attr.user | gdt_attr.writable
-    at GDTEntry.flags__limith, db 0
-    at GDTEntry.baseh, db 0
-iend
-
 ; All GTD addresses are multiples of 8,
 ; and thus end in three zero bits.
 ;