86 lines
1.6 KiB
Typst
86 lines
1.6 KiB
Typst
#import "@local/handout:0.1.0": *
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#show: handout.with(
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title: [Warm-Up: Adders],
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by: "Mark",
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)
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#problem()
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Fill the following binary addition table. \
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#hint([s is "sum," c is "carry"])
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#align(
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center,
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table(
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columns: (9mm, 9mm, 9mm, 9mm),
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align: center,
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$a$, $b$, $s$, $c$,
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[0], [0], [?], [?],
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[0], [1], [?], [?],
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[1], [0], [?], [?],
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[1], [1], [?], [?],
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),
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)
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#v(1fr)
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#problem()
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Draw a logic circuit that atisfies the above table. \
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This is called a _half adder_. \
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#hint([You should need exactly two gates.])
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#solution([
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$s = a #text([`xor`]) b$ \
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$c = a #text([`and`]) b$
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])
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#v(1fr)
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#definition()
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A _full adder_ is similar to a half adder, but it has an extra input: \
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a full adder takes $a$, $b$, and $c_"in"$, and produces $s$ and $c_"out"$. \
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#hint([$c_"in"$ is "carry in"])
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#problem()
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Use two half adders to construct a full adder.
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#solution([
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$
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s_1, c_1 &= "HA"(a, b) \
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s_2, c_2 &= "HA"(s_1, c_"in") \
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s_"out" &= s_2 \
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c_"out" &= "OR"(c_1, c_2)
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$
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#v(2mm)
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Of course, the class should just draw the circuit.
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])
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#v(1fr)
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#pagebreak()
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#problem(label: "ripple-adder")
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How can we add two four-bit binary numbers using the full adder? \
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We want a four-bit output sum and a one-bit $c_"out"$.
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#v(1fr)
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#problem()
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Say that all basic logic gates need $1u$ of time to fully switch states. \
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#note([This is called _gate delay_], type: "Note")
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#v(2mm)
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How much time does a full adder need to fully switch states? \
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How about your circuit from @ripple-adder?
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#v(1fr)
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#problem("Bonus")
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Design a faster solution to @ripple-adder.
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#v(1fr)
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