#import "@local/handout:0.1.0": *

#show: handout.with(
  title: [Warm-Up: Adders],
  by: "Mark",
)

#problem()
Fill the following binary addition table. \
#hint([s is "sum," c is "carry"])

#align(
  center,
  table(
    columns: (9mm, 9mm, 9mm, 9mm),
    align: center,
    $a$, $b$, $s$, $c$,
    [0], [0], [?], [?],
    [0], [1], [?], [?],
    [1], [0], [?], [?],
    [1], [1], [?], [?],
  ),
)

#v(1fr)

#problem()
Draw a logic circuit that atisfies the above table. \
This is called a _half adder_. \
#hint([You should need exactly two gates.])

#solution([
  $s = a #text([`xor`]) b$ \
  $c = a #text([`and`]) b$
])

#v(1fr)

#definition()
A _full adder_ is similar to a half adder, but it has an extra input: \
a full adder takes $a$, $b$, and $c_"in"$, and produces $s$ and $c_"out"$. \
#hint([$c_"in"$ is "carry in"])

#problem()
Use two half adders to construct a full adder.

#solution([
  $
    s_1, c_1 &= "HA"(a, b) \
    s_2, c_2 &= "HA"(s_1, c_"in") \
    s_"out" &= s_2 \
    c_"out" &= "OR"(c_1, c_2)
  $

  #v(2mm)

  Of course, the class should just draw the circuit.
])


#v(1fr)
#pagebreak()



#problem(label: "ripple-adder")
How can we add two four-bit binary numbers using the full adder? \
We want a four-bit output sum and a one-bit $c_"out"$.
#v(1fr)

#problem()
Say that all basic logic gates need $1u$ of time to fully switch states. \
#note([This is called _gate delay_], type: "Note")

#v(2mm)

How much time does a full adder need to fully switch states? \
How about your circuit from @ripple-adder?

#v(1fr)

#problem("Bonus")
Design a faster solution to @ripple-adder.

#v(1fr)