From c2672e135b2bb827a17e8f0bff937b1e0851368c Mon Sep 17 00:00:00 2001
From: Mark <mark@betalupi.com>
Date: Sat, 27 Jan 2024 13:02:53 -0800
Subject: [PATCH] Added adder handout

---
 Misc/Warm-Ups/adders.tex | 92 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100755 Misc/Warm-Ups/adders.tex

diff --git a/Misc/Warm-Ups/adders.tex b/Misc/Warm-Ups/adders.tex
new file mode 100755
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@@ -0,0 +1,92 @@
+\documentclass[
+	solutions,
+	singlenumbering,
+	nopagenumber
+]{../../resources/ormc_handout}
+\usepackage{../../resources/macros}
+
+
+\title{Warm-Up: Adders}
+\subtitle{Prepared by \githref{Mark} on \today}
+
+\begin{document}
+
+	\maketitle
+
+	\problem{}
+	Fill the following binary addition table. \par
+	\hint{s is \say{sum,} c is \say{carry}}
+
+	\begin{center}
+		\begin{tabular}{ c c || c c }
+			$a$ & $b$ & s & c \\
+			\hline
+			0 & 0 & ? & ? \\
+			0 & 1 & ? & ? \\
+			1 & 0 & ? & ? \\
+			1 & 1 & ? & ?
+		\end{tabular}
+	\end{center}
+
+	\vfill
+
+	\problem{}
+	Draw a logic circuit that atisfies the above table. \par
+	This is called a \textit{half adder}. \par
+	\hint{You should need exactly two gates.}
+
+	\begin{solution}
+		$s = a \texttt{ xor } b$ \par
+		$c = a \texttt{ and } b$
+	\end{solution}
+
+	\vfill
+
+	\definition{}
+	A \textit{full adder} is similar to a half adder, but it has an extra input: \par
+	a full adder takes $a$, $b$, and $c_\text{in}$, and produces $s$ and $c_\text{out}$. \par
+	\hint{$c_\text{in}$ is \say{carry in}}
+
+	\problem{}
+	Use two half adders to construct a full adder.
+
+	\begin{solution}
+		$s_1, c_1 = \texttt{HA}(a, b)$ \par
+		$s_2, c_2 = \texttt{HA}(s_1, c_\text{in})$ \par
+		$s_\text{out} = s_2$ \par
+		$c_\text{out} = \texttt{OR}(c_1, c_2)$
+
+		\vspace{2mm}
+
+		Of course, the class should just draw the circuit.
+	\end{solution}
+
+
+	\vfill
+	\pagebreak
+
+	\problem{}<rippleadder>
+	How can we add two four-bit binary numbers using the full adder? \par
+	We want a four-bit output sum and one-bit $c_\text{out}$.
+
+	\vfill
+
+	\problem{}
+	Say that all basic logic gates need $1u$ of time to fully switch states. \par
+	\note[Note]{This is called \textit{gate delay}}
+
+	\vspace{2mm}
+
+	How much time does a full adder need to fully switch states? \par
+	How about your circuit from \ref{rippleadder}?
+
+	\vfill
+
+	\problem{Bonus}
+	Design a faster solution to \ref{rippleadder}.
+
+
+	\vfill
+	\pagebreak
+
+\end{document}
\ No newline at end of file